1. Field of the Invention
The present invention relates to an integrated circuit having a comparator circuit including at least one differential amplifier, and more particularly to an integrated circuit having a comparator, which is adaptable for a 1-bit A/D convertor or a digitizing circuit for translating the output signals of sensors, entering keys, or the like, and delivering a control signal to a switch for controlling a load.
2. Discussion of the Related Art
Output signals received from sensors, entering keys, or the like, which are treated as digital signals, may be considered to be, in the strict sense, analog signals having gentle rise profiles. Before such output signals are supplied to post-processing by a microcomputer, for example, the output signals must be converted into normal digital Signals (binary logic signals) with high precision by a 1-bit A/D converter or a quantizing circuit. It is a common practice to use a buffer circuit for the digitizing circuit or the quantizing circuit. The buffer circuit has a unique threshold value. Because of this, the timing of changes in the logic level of the digital signal is unconditionally determined and fixed by the threshold value of the buffer circuit. As a result, it is impossible to adjust the rise point and the fall point of the digital signal. To cope with this, it is desirable to use a comparator constructed using a differential amplifier circuit of high gain. In this respect, there has been demanded the development of a semiconductor integrated circuit containing a plurality of comparators of that type in order to digitize a plurality of signals.
A conventional comparator using a high-gain differential amplifier circuit is shown in FIG. 12. As shown, the comparator is made up of a current mirror circuit M, a differential amplifier circuit S.sub.1 with two current paths L.sub.1 and L.sub.2, and an inverter INV. The output section of the current mirror circuit operates as a constant current source for the differential amplifier circuit.
A drain current i.sub.0 of an enhancement type (E-type) MOS transistor 2 flows, as a reference current, from a voltage source V.sub.DD to the input section of the current mirror circuit M, through a load MOS transistor 1 of the depletion type (D-type). A drain current i.sub.3, which depends on the reference current i.sub.0, flows through an E-type MOS transistor 10 in the output section.
In the first current path L.sub.1 of the differential amplifier circuit S.sub.1, a drain current i.sub.1, flows from the voltage source V.sub.DD and passes through a D-type MOS transistor 11, which serves as a load transistor, and an E-type MOS transistor 15, which serves as an amplifying transistor. In the second current path L.sub.2, a drain current i.sub.2 flows from the voltage source V.sub.DD and passes through a D-type MOS transistor 12, which serves as a load transistor, and an E-type MOS transistor 16, which serves as an amplifying transistor. The gates of the amplifying transistors 15 and 16 are respectively connected to input terminals in1 and in2 as the input terminals of the differential amplifier circuit S.sub.1. The current paths L.sub.1 and L.sub.2 are connected to the output section (as a constant current source) of the current mirror circuit M. Accordingly, the following equation holds: EQU i.sub.3 =i.sub.1 +i.sub.2 (1)
When the voltage applied to the input terminal in1 is equal to the voltage applied to the input terminal in2, the following equation holds: EQU i.sub.1 =i.sub.2.sub.3 /2 (2)
Under this condition, the differential amplifier circuit S.sub.1 is in a balanced state.
When the voltage (input voltage V.sub.in) applied to the input terminal in2 is higher than the voltage (reference voltage V.sub.ref) applied to the input terminal in1, the current i.sub.2 flowing through the MOS transistor 16 is increased by an increment .DELTA.i, which depends on the difference between the input voltages. Correspondingly, the current i.sub.1 flowing into the MOS transistor 15 is decreased by .DELTA.i, as seen from the equation (1). A voltage drop across the load transistor 12 increases and the source potential (potential at node 102) consequently drops.
When the input voltage V.sub.in is lower than the reference voltage V.sub.ref, the voltage drop across the load transistor 12 decreases and the source potential (potential at node 102) rises. Accordingly, the potential (at node 102) of the load transistor 12 is the amplified voltage, which depends on the difference between the voltages applied to the input terminals in1 and in2, with the balancing voltage being the voltage drop caused by the balancing current (i.sub.3 /2).
The inverter INV is made up of a MOS transistor 4, which serves as a switching element, and a MOS transistor 3, which serves as a load transistor, wherein both the MOS transistor 3 and the MOS transistor 4 are connected in series. The gate of the MOS transistor 4 receives the output voltage (differential amplifier voltage) V.sub.102 present at the node 102. The inverter INV produces a digitized signal V.sub.OUT as a binary signal having a high or low logic level which depends on the amplitude of the input voltage V.sub.in relative to that of the reference voltage V.sub.ref. As recalled, the input voltage V.sub.in is applied to the input terminal in2 and the reference voltage V.sub.ref to the input terminal in1.
FIG. 13(a) is a graph showing variations of the input potentials (V.sub.in and the reference voltage V.sub.ref) of the differential amplifier circuit S.sub.1 with respect time t wherein the reference voltage V.sub.ref at the input terminal in1 is higher than the respective threshold voltages V.sub.th15 and V.sub.th16 of the amplifying transistors 15 and 16. At point A, the reference voltage V.sub.ref is equal to the input voltage V.sub.in (V.sub.ref =V.sub.in). At point P, the input voltage V.sub.in is equal to the threshold voltages V.sub.th15 and V.sub.th16. FIG. 13(b) is a graph showing variations of the output voltages (voltage V.sub.101 at node 101 and voltage V.sub.102 at node 102) of the differential amplifier circuit S.sub.1 with respect to units of time t corresponding to the units of time of FIG. 13(a) wherein the input voltages of differential amplifier circuit S.sub.1 are those shown in FIG. 13(a). A line consisting of alternating long and two short dashes indicates the threshold voltage V.sub.th4 of the MOS transistor 4. Point B indicates a voltage balanced state (V.sub.101 =V.sub.102), which corresponds to the voltage balanced state at point A. At point C, the voltage V.sub.102 at the node 102 is equal to the threshold voltage V.sub.th4.
When the input voltage V.sub.in is lower than the threshold voltages V.sub.th15 and V.sub.th16 the amplifying MOS transistor 16 is in an off state, and the amplifying MOS transistor 15 is in an on state. The node 102 is pulled up to the source potential V.sub.DD, and the voltage V.sub.101 at the node 101 is in the lowest level V.sub.LOW. When the input voltage V.sub.in exceeds the threshold voltages V.sub.th15 and V.sub.th16, the amplifying MOS transistor 16 is also turned on, a normal differentially amplified output signal is present at the nodes 101 and 102. When the input voltage V.sub.in is lower than the threshold voltages V.sub.th15 and V.sub.th16, the output signal of the differential amplifier circuit S.sub.1, in the strict sense, is not the output signal when the differential amplifier circuit operates as a linear differential amplifier. However, this is not problematic in the digitizing operation because under this condition, the amplifier circuit has output characteristics which depend upon the input voltage difference.
In the case where the input voltage V.sub.in is lower than the threshold voltages V.sub.th15 and V.sub.th16, the circuit shown in FIG. 12 exhibits the following problems. FIG. 14(a) is a graph showing variations of the input potentials (V.sub.in and the reference voltage V.sub.ref) of the differential amplifier circuit S.sub.1 with respect to time t wherein the reference voltage V.sub.ref at the input terminal in1 is lower than the threshold voltages V.sub.th15 and V.sub.th16 of the amplifying transistors 15 and 16. At point A, the reference voltage V.sub.ref is equal to the input voltage V.sub.in. At point P, the input voltage V.sub.in is equal to the threshold voltages V.sub.th15 and V.sub.th16. FIG. 14(b) is a graph showing variations of the output voltages (voltage V.sub.101 at node 101 and voltage V.sub.102 at node 102) of the differential amplifier circuit S.sub.1 with respect to units of time t corresponding to the units of time of FIG. 14(a) wherein the input voltages V.sub.in and V.sub.ref of differential amplifier circuit S.sub.1 are those shown in FIG. 14(a). When the input voltage V.sub.in is lower than the threshold voltages V.sub.th15 and V.sub.th16, the amplifying MOS transistors 16 and 15 are both in an off state. Accordingly, the nodes 101 and 102 are both pulled up to the source potential V.sub.DD. When the MOS transistors 16 and 15 are both inoperable in this low level region, and there is a voltage difference present between the input voltage V.sub.in and the reference voltage V.sub.ref, a differentially amplified output signal based on the voltage difference cannot be obtained. In other words, when the reference voltage V.sub.ref is set to be lower than the threshold voltages V.sub.th15 and V.sub.th16, the differential amplifier circuit loses its differential amplifying function for the input voltage V.sub.in within the low level region, and consequently it loses its digitizing function.
FIG. 13(c) is a graph showing variations of the output voltage V.sub.OUT of the inverter INV with respect to units of time t corresponding to the units of time of FIGS. 13(a) and 13(b) wherein the input voltages V.sub.in and V.sub.ref of differential amplifier circuit S.sub.1 are those shown in FIG. 13(a) and wherein the reference voltage V.sub.ref at the input terminal in1 is higher than the threshold voltages V.sub.th15 and V.sub.th16 of the amplifying transistors 15 and 16. When the input voltage V.sub.in rises from ground potential, the voltage V.sub.102 at the node 102 falls, as seen from FIG. 13(b). When the voltage V.sub.102 falls and its locus crosses the level of the threshold voltage V.sub.th4 (point C) of the MOS transistor 4, the output voltage V.sub.OUT of the inverter INV rises from a low potential level (referred to as an L level) to a high potential level (referred to as an H level). The balancing potential (point B) of the differential amplifier circuit S.sub.1 is determined by the element characteristics of the differential amplifier circuit S.sub.1. The threshold voltage V.sub.th4 (point C) is a property of the MOS transistor 4 of the subsequent stage which depends, for example, on the semiconductor fabricating process used to produce MOS transistor 4. Therefore, the points B and C are generally not coincident with each other in position, and it is almost impossible to coincide point B with point C. For this reason, the logic level of the V.sub.OUT remains unchanged until the input voltage V.sub.in exceeds the reference voltage V.sub.ref plus an offset voltage V.sub.off2. Presence of the offset voltage V.sub.off2 owing to the threshold voltage of the inverter INV brings about retardation (phase delay) of the rise or advancement (phase advancement) of the fall of the output digital signal with respect to the input voltage V.sub.in, and formation of an insensitive region for digitalization.
FIG. 14(c) is a graph showing variations of the output voltage V.sub.OUT of the inverter INV with respect to units of time t corresponding to the units of time of FIGS. 14(a) and 14(b) wherein the input voltages V.sub.in and V.sub.ref of differential amplifier circuit S.sub.1 are those shown in FIG. 14(a) and wherein the reference voltage V.sub.ref at the input terminal in1 is lower than the threshold voltages V.sub.th15 and V.sub.th16 of the amplifying transistors 15 and 16. Since the reference voltage V.sub.ref is lower than the threshold voltage V.sub.th15,16 of the amplifying MOS transistor 15, the transistor is always in an off state. When the input voltage V.sub.in rises from the ground potential, and reaches the threshold voltage V.sub.th15,16, the MOS transistor 16 is turned on and the output voltage V.sub.102 at the node 102 becomes a low voltage V.sub.LOW. The transistor 4 connected to the node 102 is then turned on, so that the output voltage V.sub.OUT of the inverter INV rises from an L level to an H level. Although the output voltage V.sub.OUT takes a digital form, the logic level changing point of the output voltage is determined by the threshold voltages V.sub.th15,16 which are properties of the MOS transistors. When the input voltage V.sub.in exceeds the reference voltage V.sub.ref, the logic state of the output voltage V.sub.OUT remains unchanged. When the input voltage V.sub.in exceeds the reference voltage V.sub.ref plus an offset voltage V.sub.off1, the output voltage V.sub.OUT changes. Presence of the offset voltage V.sub.off1 owing to the threshold voltage of the differential amplifier circuit S.sub.1 also brings about retardation (phase delay) of the rise or advancement (phase advancement) of the fall of the output digital signal with respect to the input voltage V.sub.in, and formation of an insensitive region for digitalization.
The dependency of the offset voltage V.sub.off2 on the reference voltage V.sub.ref now will be described. First, consider the balancing potential of the amplifying voltages V.sub.101 and V.sub.102 at which the references voltage V.sub.ref is equal to the input voltage V.sub.in, and the differential amplifier circuit S.sub.1 is in a balanced state. In the current path L.sub.1 of the differential amplifier circuit S.sub.1 shown in FIG. 12, when the reference voltage V.sub.ref increases, the impedance of the MOS transistor 15 decreases. At this time, in order to compensate for a fixed balancing current (i.sub.3 /2) flowing through the MOS transistor 10, which serves as the constant current source, the impedance of the load transistor 11 increases. As a result, the voltage drop across the load transistor 11 increases, and the potential V.sub.101 at the node 101 falls. Accordingly, as the reference voltage V.sub.ref increases, the amplified voltages V.sub.101 and V.sub.102 decrease. That is, the balancing potential is varied. Accordingly, as shown in FIG. 13(a), when the reference voltage V.sub.ref is at first higher than the threshold voltages V.sub.th15 and V.sub.th16 of the MOS transistors 15 and 16, and then is decreased, the voltage at point A (V.sub.in =V.sub.ref) drops. With this, the potential at point B (V.sub.101 =V.sub.102) which represents the balancing potential of the differential amplifier circuit S.sub.1, also changes. When the balancing potential at point B changes, the offset voltage V.sub.off2, which represents a voltage to be added to the one of the input voltages V.sub.in or V.sub.ref such that the output voltage V.sub.OUT changes logic levels when at a time when V.sub.in =V.sub.ref, also changes. Thus, the offset voltage V.sub.off2 depends on the reference voltage V.sub.off2 the differential amplifier circuit S.sub.1. In other words, V.sub.off2 cannot be determined by only the threshold voltage of the inverter INV. This fact implies that when the reference voltage V.sub.ref is lowered to approach to the threshold voltage V.sub.th15,16 in order to operate the differential amplifier circuit in the low level region, the retardation (phase delay) of the rise of the output digitized signal with respect to the input voltage V.sub.in, and the like increase, impairing the digitalization precision.
FIG. 15 shows an integrated circuit 400 having a comparator circuit 405 for controlling a switch element 410, which either permits or prevents a load current from flowing through a load 420, which may consist of a coil, via a voltage source 421. Typically, switch element 410 is a vertical voltage control switch element, such as a power MOSFET that may consist of an n channel DMOS (NDMOS).
When utilizing a conventional comparator circuit, such as that shown in FIG. 12, as the comparator circuit 405 in the integrated circuit 400 shown in FIG. 15, a problem arises due to the presence of PMOS and NMOS transistors in the conventional self-isolation CMOS comparator circuit.
FIG. 16 shows a cross-section of integrated circuit 450 constructed utilizing a comparator circuit 455 including both PMOS (460) and NMOS (470) transistors and a vertical voltage control switch element 480 all formed on an n.sup.- epitaxial layer 490, which is formed on an n.sup.+ substrate 491. PMOS transistor 460 includes p-type source and drain diffusion layers 462 formed in the surface of n.sup.- epitaxial layer 490, and a gate electrode 465 formed on a gate insulation film (not shown) bridging source and drain diffusion layers 462. NMOS transistor 470 includes a p-type base layer 471 formed in the surface of n.sup.- epitaxial layer 490, n-type source and drain diffusion layers 472 formed in the surface of p-type base layer 471, and a gate electrode 475 formed on a gate insulation film (not shown) bridging source and drain diffusion layers 472. Vertical voltage control switch element 480 includes a p-type base layer 481 formed in the surface of n.sup.- epitaxial layer 490, n-type source diffusion layers 482 formed in the surface of p-type base layer 481, gate electrodes 485 formed on a gate insulation film (not shown), and a drain electrode 486 connected to the opposite surface of n.sup.+ substrate 491.
If such an integrated circuit is prepared as shown in FIG. 16, the circuit cannot be operated due to the forward bias present at the p-n junction between epitaxial layer 490 and p-type source diffusion layer 462 of PMOS transistor 460. The forward bias results from the 0.1 volt on-state voltage of the vertical voltage control switch 490, which produces a potential of 0.1 V in n.sup.- epitaxial layer 490. When this forward bias is present, comparator circuit 455 cannot supply a normal gate voltage to the gate of vertical voltage control switch 480.
Thus, to operate a comparator circuit of the type shown in FIG. 12 in the integrated circuit shown in FIG. 15, the integrated circuit must be designed to include isolation layers between the comparator circuit 455 and vertical voltage control switch 480. An example of such an integrated circuit is shown in FIG. 17 and is generally designated by reference numeral 550.
Integrated circuit 550 includes a comparator circuit 555 including both PMOS (560) and NMOS (570) transistors and a vertical voltage control switch element 580 all formed on a p-type substrate 590. PMOS transistor 560 includes p-type source and drain diffusion layers 562 formed in the surface of a first n-type epitaxial layer 591, and a gate electrode 565 formed on a gate insulation film 566 bridging source and drain diffusion layers 562. NMOS transistor 570 includes a p-type base layer 571 formed in the surface of first n-type epitaxial layer 591, n-type source and drain diffusion layers 572 formed in the surface of p-type base layer 571, and a gate electrode 575 formed on gate insulation film 566 bridging source and drain diffusion layers 572. Vertical voltage control switch element 580 includes a p-type base layers 581 formed in the surface of a second n-type epitaxial layer 592, n-type source diffusion layers 582 formed in the surface of one of the p-type base layers 581, gate electrodes 585 formed on gate insulation film 566 bridging p-type base layers 581, and an n-type drain diffusion layer 595. By providing two separate n-type epitaxial layers 591 and 592 isolated by a portion of p-type substrate 590 for comparator circuit 555 and vertical voltage control switch 580, the p-n junction between first n-type epitaxial layer 591 and p-type source diffusion layer 562 of PMOS transistor 560 will remain inverse biased and comparator circuit 555 can supply a normal gate voltage to the gate of vertical voltage control switch 580.
However, the integrated circuit design shown in FIG. 17 is disadvantageous in that the isolating portions of the substrate make manufacturing and miniaturization difficult. Because the use of PMOS transistors in the comparator circuit necessitate the use of isolation layers, it is preferable to not use PMOS transistors in the comparator circuit to avoid such problems.